Altera cyclone V Technical Reference page 472

7-24
L3 (NIC-301) GPV Registers Address Map
Security Register Group
Register
l4main on page 7-35
l4sp on page 7-37
l4mp on page 7-40
l4osc1 on page 7-43
l4spim on page 7-45
stm on page 7-47
lwhps2fpgaregs
page 7-48
usb1 on page 7-49
nanddata on page 7-
50
usb0 on page 7-51
nandregs on page 7-
52
qspidata on page 7-
53
fpgamgrdata
7-54
hps2fpgaregs
7-55
acp on page 7-56
rom on page 7-57
ocram on page 7-58
sdrdata on page 7-59
ID Register Group
Register
periph_id_4
7-60
periph_id_0
7-61
Altera Corporation
Offset
0x8
0xC
0x10
0x14
0x18
0x1C
on 0x20
0x28
0x2C
0x80
0x84
0x88
on page 0x8C
on page 0x90
0x94
0x98
0x9C
0xA0
Offset
on page 0x1FD0
on page 0x1FE0
Width Acces Reset Value
s
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
32 WO 0x0
Width Acces Reset Value
s
32 RO 0x4
32 RO 0x1
Description
L4 main peripherals security
L4 SP Peripherals Security
L4 MP Peripherals Security
L4 OSC1 Peripherals Security
L4 SPIM Peripherals Security
STM Peripheral Security
LWHPS2FPGA AXI Bridge
Registers Peripheral Security
USB1 Registers Peripheral
Security
NAND Flash Controller Data
Peripheral Security
USB0 Registers Peripheral
Security
NAND Flash Controller Registers
Peripheral Security
QSPI Flash Controller Data
Peripheral Security
FPGA Manager Data Peripheral
Security
HPS2FPGA AXI Bridge Registers
Peripheral Security
MPU ACP Peripheral Security
ROM Peripheral Security
On-chip RAM Peripheral Security
SDRAM Data Peripheral Security
Description
Peripheral ID4 Register
Peripheral ID0 Register
System Interconnect
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cv_5v4
2016.10.28