Altera cyclone V Technical Reference page 797

cv_5v4
2016.10.28
Offset:
0x5048
Access:
RW
31 30
15 14
erraddr Fields
Bit
31:0
addr
dropcount
This register holds the address of the most recent ECC error.
Module Instance
sdr
Offset:
0x504C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
SDRAM Controller Subsystem
Send Feedback
29 28 27 26
13 12 11 10
Name
The address of the most recent ECC error.
Note: For a 32-bit interface, ECC is calculated across
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
addr
RW 0x0
9 8 7 6
addr
RW 0x0
Description
a span of 8 bytes, meaning the error address is
a multiple of 8 bytes (4 bytes*2 burst length).
To find the byte address of the word that
contains the error, you must multiply the value
in the erraddr register by 8.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
dropcount
21 20 19 18
5 4 3 2
Access
Register Address
0xFFC2504C
21 20 19 18
5 4 3 2
corrdropcount
RW 0x0
11-59
17 16
1 0
Reset
RW 0x0
17 16
1 0
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