Altera cyclone V Technical Reference page 836

cv_5v4
2016.10.28
Consider the following points when using the DMA:
• A data DMA command is a type of MAP10 command. This command is interpreted by the data DMA
engine and not by the flash controller core.
• No MAP01, MAP00, or MAP11 commands are allowed when DMA is enabled.
• Before the flash controller can accept data DMA commands, DMA must be enabled by setting the
bit of the
• When DMA is enabled and the DMA engine initiates data transfers, ECC can be enabled for as-needed
data correction concurrent with the data transfer.
• MAP10 commands are used along with data movements similar to MAP01 commands.
• With the exception of data DMA commands and MAP10 pipeline read and write commands, all other
MAP10 commands such as erase, lock, unlock, and copy-back are forwarded to the flash controller.
• At any time, up to four outstanding data DMA commands can be handled by flash controller. During
multi-page operations, the DMA transfer must not cross a flash block boundary. If it does, the flash
controller generates an unsupported command (
• Data DMA commands are typically multi-page read and write commands with an associated pointer in
host memory. The multi-page data is transferred to or from the host memory starting from the host
memory pointer.
• Data DMA uses the
to drive on the interconnect. The data DMA hardware does not account for the interconnect's
boundary crossing restrictions. The host must initialize the starting host address so that the DMA
master burst transaction does not cross a 4 KB boundary.
There are two methods for initiating a DMA transaction: the multitransaction DMA command, and the
burst DMA command.
Multi-Transaction DMA Command
The NAND flash controller processes multitransaction DMA commands only if it receives all four
command-data pairs in order. The flash controller responds to out-of-order commands with an
unsup_cmd
commands are interleaved with other flash controller MAP commands.
To initiate DMA with a multitransaction DMA command, you send four command-data pairs to the
NAND flash controller through the Control and Data registers in the
"Command-Data Pair Formats".
Related Information
Command-Data Pair Formats
NAND Flash Controller
Send Feedback
register in the
dma_enable
flash_burst_length
interrupt. The flash controller also responds with an
on page 13-16
Multi-Transaction DMA Command
group.
dma
) interrupt and drops the command.
unsup_cmd
register in the
dma
unsup_cmd
group to determine the burst length value
interrupt if sequenced
region, as shown in
nanddata
13-15
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