Altera cyclone V Technical Reference page 860

cv_5v4
2016.10.28
Register
dma_intr_en on page
13-119
target_err_addr_lo
page 13-119
target_err_addr_hi
page 13-120
flash_burst_length
page 13-120
chip_interleave_enabl
e_and_allow_int_reads
on page 13-121
no_of_blocks_per_lun
on page 13-122
lun_status_cmd
page 13-123
Configuration registers Register Descriptions
Common across all types of flash devices, configuration registers setup the basic operating modes of the
controller
Offset:
0x0
device_reset
Device reset. Controller sends a RESET command to device. Controller resets bit after sending command
to device
transfer_spare_reg
Default data transfer mode. (Ignored during Spare only mode)
load_wait_cnt
Wait count value for Load operation
program_wait_cnt
Wait count value for Program operation
erase_wait_cnt
Wait count value for Erase operation
int_mon_cyccnt
Interrupt monitor cycle count value
rb_pin_enabled
Interrupt or polling mode. Ready/Busy pin is enabled from device.
multiplane_operation
Multiplane transfer mode. Pipelined read, copyback, erase and program commands are transfered in
multiplane mode
NAND Flash Controller
Send Feedback
Offset Width Acces
0x730 32
on 0x740 32
on 0x750 32
on 0x770 32
0x780 32
0x790 32
on 0x7A0 32
on page 13-41
on page 13-42
on page 13-43
on page 13-44
on page 13-45
on page 13-46
on page 13-47
on page 13-48
Configuration registers Register Descriptions
Reset Value
s
RW 0x0
RO 0x0
RO 0x0
RW 0x1
RW 0x10
RW 0xF
RW 0x7878
13-39
Description
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