Altera cyclone V Technical Reference page 807

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
highaddr
RW 0x0
protruleaddr Fields
Bit
23:12
highaddr
11:0
lowaddr
protruleid
This register configures the AxID for a given protection rule.
Module Instance
sdr
Offset:
0x5094
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
SDRAM Controller Subsystem
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
Name
Upper 12 bits of the address for a check. Address is
compared to be greater than or equal to the address of
a transaction. Note that since AXI transactions
cannot cross a 4K byte boundary, the transaction start
and transaction end address must also fall within the
same 1MByte block pointed to by this address pointer.
Lower 12 bits of the address for a check. Address is
compared to be less than or equal to the address of a
transaction. Note that since AXI transactions cannot
cross a 4K byte boundary, the transaction start and
transaction end address must also fall within the same
1MByte block pointed to by this address pointer.
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
9 8 7 6
lowaddr
RW 0x0
Description
Base Address
protruleid
21 20 19 18
highaddr
RW 0x0
5 4 3 2
Access
Register Address
0xFFC25094
11-69
17 16
1 0
Reset
RW 0x0
RW 0x0
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