Altera cyclone V Technical Reference page 512

7-64
comp_id_0
periph_id_3 Fields
Bit
7:4
rev_and
3:0
cust_mod_num
comp_id_0
Component ID0
Module Instance
l3regs
Offset:
0x1FF0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
comp_id_0 Fields
Bit
7:0
preamble
comp_id_1
Component ID1
Module Instance
l3regs
Offset:
0x1FF4
Altera Corporation
Name
Revision
Customer Model Number
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Preamble
Description
Base Address
0xFF800000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFF800000
Access
Register Address
0xFF801FF0
21 20 19 18
5 4 3 2
preamble
RO 0xD
Access
Register Address
0xFF801FF4
System Interconnect
cv_5v4
2016.10.28
Reset
RO 0x0
RO 0x0
17 16
1 0
Reset
RO 0xD
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