Altera cyclone V Technical Reference page 509

Hard processor system
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cv_5v4
2016.10.28
Offset:
0x1FD0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
periph_id_4 Fields
Bit
7:0
periph_id_4
periph_id_0
Peripheral ID0
Module Instance
l3regs
Offset:
0x1FE0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
System Interconnect
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Name
JEP106 continuation code
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Description
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
periph_id_0
21
20
19
18
5
4
3
2
periph_id_4
RO 0x4
Access
Register Address
0xFF801FE0
21
20
19
18
5
4
3
2
pn7to0
RO 0x1
7-61
17
16
1
0
Reset
RO
0x4
17
16
1
0
Altera Corporation

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