Altera cyclone V Technical Reference page 76

cv_5v4
2016.10.28
dbgatclk
Contains settings that control clock dbg_base_clk generated from the C2 output of the Main PLL. Only
reset by a cold reset.
Module Instance
clkmgr
Offset:
0x50
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
dbgatclk Fields
Bit
8:0
cnt
mainqspiclk
Contains settings that control clock main_qspi_clk generated from the C3 output of the Main PLL. Only
reset by a cold reset.
Module Instance
clkmgr
Offset:
0x54
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Clock Manager
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0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Divides the VCO/4 frequency by the value+1 in this
field.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
dbgatclk
Register Address
0xFFD04050
21 20 19 18
5 4 3 2
cnt
RW 0x0
Access
Register Address
0xFFD04054
2-39
17 16
1 0
Reset
RW 0x0
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