Document Revision History - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Register Group
Address Filtering
Reserved
Debug, Prefetch,
Power
Related Information
Cortex-A9 MPCore Technical Reference Manual
For more information about the use of the L2 Cache Controller address space, refer to the Cortex-A9
MPCore Technical Reference Manual, available on the ARM Infocenter website.

Document Revision History

Date
October 2016
May 2016
November 2015
May 2015
Cortex-A9 Microprocessor Unit Subsystem
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Description
This address space is
allocated for address
filtering registers.
This address space is
reserved.
This address space is
allocated for debug,
prefetch and power
registers.
Version
2016.10.28
• Added note to "AXI Master Configuration for ACP Access" section
• Added "Configuring
"Configuring
"AXI Master Configuration for ACP Access" section
• Added note in the "Implementation Details" subsection of the "ACP
ID Mapper" section.
2016.05.03 Maintenance release
2015.11.02
• Reordered "L2 Cache" subsections
• Renamed "ECC Support" L2 subsection to be "Single Event Upset
Protection"
• Added "L2 Cache Parity" subsection in "L2 Cache" section
2015.05.04 Clarified EMAC0 and EMAC1 ACP Mapper IDs in the "HPS
Peripheral Master Input IDs" table in the "HPS Peripheral Master Input
IDs" section.
Start Address
0xFFFEFC00
0xFFFEFD00
0xFFFEFF00
Changes
AxCACHE[3:0]
] Sideband Signals" subsections to the
AxUser[4:0
Document Revision History
End Address
0xFFFEFCFF
0xFFFEFEFF
0xFFFEFFFF
Sideband Signals" and
Altera Corporation
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