Bootstrap Interface - Altera cyclone V Technical Reference

13-4

Bootstrap Interface

memory control registers, enabling it to correctly program other registers in the flash device, and goes
step
to
4. If the data does not have a valid ONFI signature, the flash controller assumes that it is a legacy
(non-ONFI) device. The flash controller then performs the following steps:
a. Sends the
b. Reads the device signature information
c. Stores the relevant values into internal memory controller registers
5. The flash controller resets the memory device. At the same time, it verifies the width of the memory
interface. The HPS supports one 8-bit NAND flash device. As a result, the flash controller always
detects an 8-bit memory interface.
6. The flash controller sends the
read access, so the processor can boot from that page. The processor can start reading from the first
page of the flash memory, which is the expected location of the pre-loader software.
Note: The system manager can bypass this step by asserting
reset is de-asserted.
7. The flash controller sends the
8. The flash controller clears the
indicate to software that the flash reset is complete.
Bootstrap Interface
The NAND flash controller provides a bootstrap interface that allows software to override the default
behavior of the flash controller. The bootstrap interface contains four bits, which when set appropriately,
allows the flash controller to skip the initialization phase and begin loading from flash memory
immediately after reset. These bits are driven by software through the system manager. They are sampled
by the NAND flash controller when the controller is released from reset.
Related Information
System Manager
For more information about the bootstrap interface control bits.
Bootstrap Setting Bits
The following table lists the relevant bootstrap setting bits, found in the system manager's
register, in the NAND flash controller register group. As an example, this table also lists recommended
bootstrap settings for a 512-byte page device.
Table 13-2: Bootstrap Setting Bits
Bit
noinit
page512
noloadb0p0
When this register is set, the NAND flash controller expects the host to program the related device parameter
(30)
registers. For more information, refer to "Configuration by Host".
Altera Corporation
5.
command to the device
reset
Page Load
reset
rst_comp
on page 5-1
command to block 0, page 0 of the device, configuring direct
bootstrap_inhibit_b0p0_load
command to the flash.
bit in the
intr_status0
Example Value for 512-Byte Page
1
register in the
status
(30)
1
1
NAND Flash Controller
cv_5v4
2016.10.28
before
group to
bootstrap
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