Altera cyclone V Technical Reference page 602

8-20
HPS2FPGA AXI Bridge Module Address Map
The HPS-to-FPGA bridge's GPV, described in "The Global Programmers View", provides settings to adjust
the bridge master properties. The master issuing capability can be adjusted, through the
allow one or multiple transactions to be outstanding in the FPGA fabric. The master bypass merge feature
can also be enabled, through the
upsizing and downsizing logic does not alter any transactions when the FPGA master interface is
configured to be 32 or 128 bits wide.
Note: It is critical to provide the correct
"GPV Clocks".
Related Information
The Global Programmers View
•
GPV Clocks
•
Functional Description of the System Interconnect
•
Detailed information about connectivity, such as which masters have access to each bridge
Cortex-A9 Microprocessor Unit Subsystem
•
Details about L2 cache address filtering
AXI Bridges
•
Information about configuring the AXI bridges
HPS2FPGA AXI Bridge Module Address Map
Registers in the HPS2FPGA AXI Bridge Module.
Base Address:
ID Register Group
Register
periph_id_4
8-22
periph_id_0
8-22
periph_id_1
8-23
periph_id_2
8-24
periph_id_3
8-24
comp_id_0 on page 8-
25
comp_id_1 on page 8-
26
comp_id_2 on page 8-
26
Altera Corporation
bypass_merge
on page 8-53
on page 27-7
0xFF500000
Offset
on page 0x1FD0
on page 0x1FE0
on page 0x1FE4
on page 0x1FE8
on page 0x1FEC
0x1FF0
0x1FF4
0x1FF8
bit in the
fn_mod2
clock to support access to the GPV, as described in
l4_mp_clk
on page 8-4
on page 9-1
Width Acces Reset Value
s
32 RO 0x4
32 RO 0x1
32 RO 0xB3
32 RO 0x6B
32 RO 0x0
32 RO 0xD
32 RO 0xF0
32 RO 0x5
fn_mod
register. This feature ensures that the
Description
Peripheral ID4 Register
Peripheral ID0 Register
Peripheral ID1 Register
Peripheral ID2 Register
Peripheral ID3 Register
Component ID0 Register
Component ID1 Register
Component ID2 Register
HPS-FPGA Bridges
cv_5v4
2016.10.28
register, to
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