Altera cyclone V Technical Reference page 997

cv_5v4
2016.10.28
middle of a block of data being transferred from the card to the host. For more information, refer to
Card Read Threshold.
Note: If the card read threshold enable bit (
RX FIFO buffer does not become full during a read data transfer by ensuring that the RX FIFO
buffer is read at a rate faster than that at which data is written into the FIFO buffer. Otherwise,
an overflow might occur.
4. Write the
5. Write the
Block Reads. For SD and MMC cards, use the SD/SDIO READ_SINGLE_BLOCK (CMD17) command
for a single-block read and the READ_MULTIPLE_BLOCK (CMD18) command for a multiple-block
read. For SDIO cards, use the IO_RW_EXTENDED (CMD53) command for both single-block and
multiple-block transfers. The command argument for (CMD53) is shown in the figure, below. After
writing to the
the bus, the Command Done interrupt is generated.
6. Software must check for data error interrupts, reported in the
rintsts
command.
7. Software must check for host timeout conditions in the
• Receive FIFO buffer data request
• Data starvation from host—the host is not reading from the FIFO buffer fast enough to keep up
with data from the card. To correct this condition, software must perform the following steps:
• Read the
• Read the corresponding amount of data out of the FIFO buffer
In both cases, the software must read data from the FIFO buffer and make space in the FIFO buffer for
receiving more data.
8. When a DTO interrupt is received, the software must read the remaining data from the FIFO buffer.
SD/MMC Controller
Send Feedback
†
†
register with the beginning data address for the data read.
cmdarg
register with the parameters listed in cmd Register Settings for Single-Block and Multiple-
cmd
register, the controller starts executing the command. When the command is sent to
cmd
register. If required, software can terminate the data transfer by sending an SD/SDIO STOP
†
field of the
fifo_count
†
Single-Block or Multiple-Block Read
) is 0, the host system must ensure that the
cardrdthren
†
rintsts
†
†
register
status
†
, , , and bits of the
dcrc bds sbe ebe
†
register:
†
14-51
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†
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