Altera cyclone V Technical Reference page 596

8-14
comp_id_3
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
comp_id_2 Fields
Bit
7:0
preamble
comp_id_3
Component ID3
Module Instance
fpga2hpsregs
Offset:
0x1FFC
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Preamble
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFF600000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
21 20 19 18
5 4 3 2
preamble
RO 0x5
Access
Register Address
0xFF601FFC
21 20 19 18
5 4 3 2
preamble
RO 0xB1
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x5
17 16
1 0
HPS-FPGA Bridges
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