Altera cyclone V Technical Reference page 220

5-26
bootinfo
Bit
1:0
mode_0
bootinfo
Provides access to boot configuration information.
Module Instance
sysmgr
Offset:
0x14
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
bootinfo Fields
Bit
9:8
pincsel
Altera Corporation
Name
Controls behavior of L4 watchdog when CPUs in
debug mode. Field array index matches L4 watchdog
index.
Value
0x0
0x1
0x2
0x3
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Specifies the sampled value of the HPS CSEL pins.
The value of HPS CSEL pins are sampled upon
deassertion of cold reset.
Description
Description
Continue normal operation ignoring debug
mode of CPUs
Pause normal operation only if CPU0 is in
debug mode
Pause normal operation only if CPU1 is in
debug mode
Pause normal operation if CPU0 or CPU1 is
in debug mode
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
pincsel pinbsel
RO 0x0 RO 0x0
Description
Access
Register Address
0xFFD08014
21 20 19 18
5 4 3 2
csel
RO 0x0
Access
cv_5v4
2016.10.28
Reset
RW 0x3
17 16
1 0
bsel
RO 0x0
Reset
RO 0x0
System Manager
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