Upsizing Data Width Function - Altera cyclone V Technical Reference

7-20

Upsizing Data Width Function

Slave
ACP ID
mapper data
STM
On-chip
boot ROM
On-chip
RAM
SDRAM
subsystem
L3 data
Related Information
FIFO Buffers and Clock Crossing
Upsizing Data Width Function
The upsizing function combines narrow transactions into wider transactions to increase the overall system
bandwidth. Upsizing only packs data for read or write transactions that are cacheable. If the interconnect
splits input-exclusive transactions into more than one output bus transaction, it removes the exclusive
information from the multiple transactions it creates.
The upsizing function can expand the data width by the following ratios:
• 1:2
• 1:4
If multiple responses from created transactions are combined into one response, then the following order
of priority applies:
•
DECERR
•
SLVERR
• is the lowest priority.
OKAY
Related Information
http://infocenter.arm.com
Additional information is available in the AMBA Network Interconnect (NIC-301) Technical Reference
Manual, revision r2p3, which you can download from the ARM Infocenter website.
Acceptance is based on the number of read, write, and total transactions.
(17)
The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth
(18)
is based on W, A, and D channels.
Altera Corporation
I/F Width Clock
64
mpu_l2_ram_clk
32
dbg_at_clk
32
l3_main_clk
64
l3_main_clk
32
l3_main_clk
is the highest priority
is the next highest priority
Mastered By
L3 interconnect
L3 interconnect
L3 interconnect
L3 interconnect
L3 interconnect
on page 7-22
Acceptance Buffer
(17)
Depth
(18)
13, 5, 18 2, 2, 2, 2, 2 AXI
1, 2, 2 2, 2, 2, 2, 2 AXI
1, 1, 2 0, 0, 0, 0, 0 AXI
2, 2, 2 0, 0, 0, 8, 0 AXI
16, 16, 16 2, 2, 2, 2, 2 AXI
System Interconnect
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cv_5v4
2016.10.28
Type