Altera cyclone V Technical Reference page 731

cv_5v4
2016.10.28
Each CTI has two interfaces, the trigger interface and the channel interface. The trigger interface is the
interface between the CTI and other components. It has eight trigger signals, which are hardwired to other
components. The channel interface is the interface between a CTI and its CTM, with four bidirectional
channels. The mapping of trigger interface to channel interface (and vice versa) in a CTI is dynamically
configured. You can enable or disable each CTI trigger output and CTI trigger input connection individu‐
ally.
For example, you can configure trigger input 0 in the FPGA-CTI to route to channel 3, and configure
trigger output 3 in the FPGA-CTI and trigger output 7 in CTI-0 in the MPU debug subsystem to route
from channel 3. This configuration causes a trigger at trigger input 0 in FPGA-CTI to propagate to trigger
output 3 in the FPGA-CTI and trigger output 7 in CTI-0. Propagation can be single-to-single, single-to-
multiple, multiple-to-single, and multiple-to-multiple.
A particular soft logic signal in the FPGA connected to a trigger input in the FPGA-CTI can be configured
to trigger a flush of trace data to the TPIU. For example, you can configure channel 0 to trigger output 2 in
the csCTI. Then configure trigger input T3 to channel 0 in FPGA-CTI. Trace data is flushed to the TPIU
when a trigger is received at trigger output 2 in the csCTI.
Another soft logic signal in the FPGA connected to trigger input T2 in FPGA-CTI can be configured to
trigger an STM message. The csCTI output triggers 4 and 5 are wired to the STM CoreSight component in
the HPS. For example, configure channel 1 to trigger output 4 in the csCTI. Then configure trigger input
T2 to channel 1 in FPGA-CTI.
Another soft logic signal in the FPGA fabric connected to trigger input T1 in FPGA-CTI can be
configured to trigger a breakpoint on CPU 1. Trigger output 1 in CTI-1 is wired to the debug request
(EDBGRQ) signal of CPU-1. For example, configure channel 2 to trigger output 1 in CTI-1. Then
configure trigger input T1 to channel 2 in FPGA-CTI.
Related Information
Coresight Component Address
•
• ARM Infocenter
For more information about the cross-trigger interface
Configuring Trigger Input 0
For example, you can configure trigger input 0 in the FPGA-CTI to route to channel 3, and configure
trigger output 3 in the FPGA-CTI and trigger output 7 in CTI-0 in the MPU debug subsystem to route
from channel 3. This configuration causes a trigger at trigger input 0 in FPGA-CTI to propagate to trigger
output 3 in the FPGA-CTI and trigger output 7 in CTI-0. Propagation can be single-to-single, single-
tomultiple, multiple-to-single, or multiple-to-multiple.
Triggering a Flush of Trace Data to the TPIU
A particular soft logic signal in the FPGA connected to a trigger input in the FPGA-CTI can be configured
to trigger a flush of trace data to the TPIU. For example, you can configure channel 0 to trigger output 2 in
csCTI. Then configure trigger input T3 to channel 0 in FPGA-CTI. Trace data is flushed to the TPIU when
a trigger is received at trigger output 2 in csCTI.
Triggering an STM message
Another soft logic signal in the FPGA connected to trigger input T2 in FPGA-CTI can be configured to
trigger an STM message. csCTI output triggers 4 and 5 are wired to the STM CoreSight component in the
CoreSight Debug and Trace
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Configuring Trigger Input 0
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