Altera cyclone V Technical Reference page 884

Hard processor system
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cv_5v4
2016.10.28
Module Instance
nandregs
Offset:
0x1B0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
ecc_correction Fields
Bit
7:0
value
read_mode
The type of read sequence that the controller will follow for pipe read commands.
Module Instance
nandregs
Offset:
0x1C0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
NAND Flash Controller
Send Feedback
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Name
The required correction capability can be a number
less than the configured error correction capability. A
smaller correction capability will lead to lesser
number of ECC check-bits being written per ECC
sector.
Base Address
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Description
0xFFB801C0
read_mode
Register Address
0xFFB801B0
21
20
19
18
5
4
3
2
value
RW 0x8
Access
Register Address
13-63
17
16
1
0
Reset
RW
0x8
Altera Corporation

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