Altera cyclone V Technical Reference page 891

13-70
max_rd_delay
rdwr_en_hi_cnt Fields
Bit
4:0
value
max_rd_delay
Max round trip read data delay for data capture
Module Instance
nandregs
Offset:
0x210
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
max_rd_delay Fields
Bit
3:0
value
Altera Corporation
Name
Number of nand_mp_clk cycles that read or write
enable will kept high to meet the min Treh/Tweh
parameter of the device. The value in this register plus
rdwr_en_lo_cnt register value should meet the min
cycle time of the device connected. The default value
is calculated assuming the max nand_mp_clk time
period of 4ns to work with ONFI Mode 0 mode of
100ns device cycle time. This assumes a 1x/4x
clocking scheme.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Number of nand_mp_clk cycles after generation of
feedback nand_mp_clk pulse when it is safe to
synchronize received data to nand_mp_clk domain.
Data should have been registered with nand_mp_clk
and stable by the time max_rd_delay cycles has
elapsed. A default value of zero will mean a value of
nand_mp_clk multiple minus one.
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Access
Register Address
0xFFB80210
21 20 19 18
5 4 3 2
Access
NAND Flash Controller
cv_5v4
2016.10.28
Reset
RW 0xC
17 16
1 0
value
RW 0x0
Reset
RW 0x0
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