Altera cyclone V Technical Reference page 156

cv_5v4
2016.10.28
Bit Name
FPGA Manager
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Description
Value
0x1 16-bit Passive Parallel with Fast Power on Reset
Delay; With AES Encryption; No Data
Compression. CDRATIO must be programmed
to x4
0x2 16-bit Passive Parallel with Fast Power on Reset
Delay; AES Optional; With Data Compression.
CDRATIO must be programmed to x8
0x3 Reserved
0x4 16-bit Passive Parallel with Slow Power on
Reset Delay; No AES Encryption; No Data
Compression. CDRATIO must be programmed
to x1
0x5 16-bit Passive Parallel with Slow Power on
Reset Delay; With AES Encryption; No Data
Compression. CDRATIO must be programmed
to x4
0x6 16-bit Passive Parallel with Slow Power on
Reset Delay; AES Optional; With Data
Compression. CDRATIO must be programmed
to x8
0x7 Reserved
0x8 32-bit Passive Parallel with Fast Power on Reset
Delay; No AES Encryption; No Data Compres‐
sion. CDRATIO must be programmed to x1
0x9 32-bit Passive Parallel with Fast Power on Reset
Delay; With AES Encryption; No Data
Compression. CDRATIO must be programmed
to x4
0xa 32-bit Passive Parallel with Fast Power on Reset
Delay; AES Optional; With Data Compression.
CDRATIO must be programmed to x8
0xb Reserved
0xc 32-bit Passive Parallel with Slow Power on
Reset Delay; No AES Encryption; No Data
Compression. CDRATIO must be programmed
to x1
0xd 32-bit Passive Parallel with Slow Power on
Reset Delay; With AES Encryption; No Data
Compression. CDRATIO must be programmed
to x4
0xe 32-bit Passive Parallel with Slow Power on
Reset Delay; AES Optional; With Data
Description
4-13
stat
Access Reset
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