Boot Rom Code - Altera cyclone V Technical Reference

5-6
USB 2.0 OTG Controller
Note: EMAC0 must be set to internal timestamp.
Related Information
Clock Manager
•
Ethernet Media Access Controller
•
USB 2.0 OTG Controller
The
usb*_l3master
master port of the USB 2.0 OTG Controller.
Note: Register bits should be accessed only when the master interface is guaranteed to be in an inactive
state.
Related Information
USB 2.0 OTG Controller
SD/MMC Controller
The
sdmmc_l3master
SD/MMC master port.
Note: Register bits should be accessed only when the master interface is guaranteed to be in an inactive
state.
You can program software to select the clock's phase shift for
setting the drive clock phase shift select (
register in the system manager.
sdmmc
Related Information
SD/MMC Controller
Watchdog Timer
The system manager controls the watchdog timer behavior when the CPUs are in debug mode. The system
manager sends a pause signal to the watchdog timers depending on the setting of the debug mode bits of
the L4 watchdog debug register (
when its associated CPU enters debug mode.
Related Information
Watchdog Timer

Boot ROM Code

Registers in the system manager control whether the boot ROM code configures the pin multiplexing for
boot pins after a warm reset. Set the warm-reset-configure-pin-multiplex for boot pins bit (
) of the boot ROM code register to enable or disable this control.
pinmux
Note: The boot ROM code always configures the pin multiplexing for boot pins after a cold reset.
Registers in the system manager also control whether the boot ROM code configures the I/O pins used
during the boot process after a warm reset. Set the warm reset configure I/Os for boot pins bit
(
warmrstcfgio
Altera Corporation
on page 2-1
on page 17-1
registers in the system manager control the
on page 18-1
register in the system manager controls the
on page 14-1
). Each watchdog timer built into the MPU subsystem is paused
wddbg
on page 24-1
) of the register to enable or disable this control.
ctrl
HPROT
cclk_in_drv
) and sample clock phase shift select (
drvsel
and fields of the USB
HAUSER
and fields of the
HPROT HAUSER
and
cclk_in_sample
smplsel
cv_5v4
2016.10.28
by
) bits of the
warmrstcfg-
System Manager
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