Altera cyclone V Technical Reference page 814

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mpweight_2_4
mpweight_1_4 Fields
Bit
31:18
sumofweights_13_0
17:0
staticweight_49_32
mpweight_2_4
This register is used to configure the DRAM burst operation scheduling.
Module Instance
sdr
Offset:
0x50B8
Access:
RW
31 30
15 14
mpweight_2_4 Fields
Bit
31:0
sumofweights_45_14
mpweight_3_4
This register is used to configure the DRAM burst operation scheduling.
Altera Corporation
Name
Set the sum of static weights for particular user
priority. This register is used as part of the deficit
round robin implementation. It should be set to the
sum of the weights for the ports
Set static weight of the port. Each port is programmed
with a 5 bit value. Port 0 is bits 4:0, port 1 is bits 9:5,
up to port 9 being bits 49:45
29 28 27 26
13 12 11 10
Name
Set the sum of static weights for particular user
priority. This register is used as part of the deficit
round robin implementation. It should be set to the
sum of the weights for the ports
Description
Base Address
0xFFC20000
Bit Fields
25 24 23 22
sumofweights_45_14
RW 0x0
9 8 7 6
sumofweights_45_14
RW 0x0
Description
Access
Register Address
0xFFC250B8
21 20 19 18
5 4 3 2
Access
SDRAM Controller Subsystem
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x0
17 16
1 0
Reset
RW 0x0
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