Altera cyclone V Technical Reference page 622

8-40
periph_id_3
31 30
15 14
periph_id_2 Fields
Bit
7:0
rev_jepcode_jep6to4
periph_id_3
Peripheral ID3
Module Instance
lwhps2fpgaregs
Offset:
0x1FEC
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
periph_id_3 Fields
Bit
7:4
rev_and
3:0
cust_mod_num
Altera Corporation
29 28 27 26
13 12 11 10
Reserved
Name
Revision, JEP106 code flag, JEP106[6:4]
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Revision
Customer Model Number
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFF400000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
rev_and
RO 0x0
Description
21 20 19 18
5 4 3 2
rev_jepcode_jep6to4
RO 0x6B
Access
Register Address
0xFF401FEC
21 20 19 18
5 4 3 2
cust_mod_num
Access
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x6B
17 16
1 0
RO 0x0
Reset
RO 0x0
RO 0x0
HPS-FPGA Bridges
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