Altera cyclone V Technical Reference page 93

2-56
en
31 30
15 14
s2fuser1clk Fields
Bit
8:0
cnt
en
Contains fields that control clock enables for clocks derived from the Peripheral PLL 1: The clock is
enabled. 0: The clock is disabled. Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0xA0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
Altera Corporation
29 28 27 26
13 12 11 10
Reserved
Name
Divides the VCO frequency by the value+1 in this
field.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
qspic nandc
lk lk
RW RW
0x1 0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
nandx sdmmc s2fus gpioc
clk clk er1cl lk
k
RW RW RW
0x1 0x1 RW 0x1
0x1
21 20 19 18
5 4 3 2
cnt
RW 0x1
Register Address
0xFFD040A0
21 20 19 18
5 4 3 2
can1c can0c spimc usbcl
lk lk lk k
RW RW RW RW
0x1 0x1 0x1 0x1
cv_5v4
2016.10.28
17 16
1 0
Access Reset
RW 0x1
17 16
1 0
emac1 emac0clk
clk
RW 0x1
RW
0x1
Clock Manager
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