Altera cyclone V Technical Reference page 795

cv_5v4
2016.10.28
dramintr Fields
Bit
4
intrclr
3
corrdropmask
2
dbemask
1
sbemask
0
intren
sbecount
This register tracks the single-bit error count.
Module Instance
sdr
Offset:
0x5040
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
SDRAM Controller Subsystem
Send Feedback
Name
Writing to this self-clearing bit clears the interrupt
signal. Writing to this bit also clears the error count
and error address registers:
dropcount
Set this bit to a one to mask interrupts for an ECC
correction write back needing to be dropped. This
indicates a burst of memory errors in a short period
of time.
Mask the double bit error interrupt.
Mask the single bit error interrupt.
Enable the interrupt output.
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
sbecount
, , and
erraddr dropaddr
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
sbecount
Access
, ,
dbecount
.
Register Address
0xFFC25040
21 20 19 18
5 4 3 2
count
RW 0x0
11-57
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
17 16
1 0
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