Altera cyclone V Technical Reference page 190

cv_5v4
2016.10.28
gpio_ver_id_code Fields
Bit
31:0
gpio_ver_id_code
gpio_config_reg2
Specifies the bit width of port A.
Module Instance
fpgamgrregs
Offset:
0x870
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
encoded_ encoded_id_pwidth_c
id_
pwidth_d
RO 0x7
gpio_config_reg2 Fields
Bit
19:15
encoded_id_pwidth_d
FPGA Manager
Send Feedback
Name
ASCII value for each number in the version, followed
by *. For example. 32_30_31_2A represents the
version 2.01
0xFF706000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
RO 0x7
Name
Specifies the width of GPIO Port D. Ignored because
there is no Port D in the GPIO.
Value
0x7
0xb
Description
Base Address
Bit Fields
25 24 23 22
9 8 7 6
encoded_id_pwidth_b
RO 0x7
Description
Description
Width (less 1) of 8 bits
Width (less 1) of 12 bits
gpio_config_reg2
Access
Register Address
0xFF706870
21 20 19 18
encoded_id_pwidth_d
RO 0x7
5 4 3 2
encoded_id_pwidth_a
RO 0xB
Access
4-47
Reset
RO 0x32303
82A
17 16
1 0
Reset
RO 0x7
Altera Corporation