Altera cyclone V Technical Reference page 467

cv_5v4
2016.10.28
Slave
DMA secure 32
CSR
DMA 32
nonsecure
CSR
SPI slave 0/1 32
Scan 32
manager
SPI master 32
0/1
Lightweight 32
HPS-to-
FPGA
bridge
USB OTG 0/ 32
1
NAND CSR 32
NAND 32
command
and data
Quad SPI 32
flash data
FPGA 32
manager
data
HPS-to- 64
FPGA
bridge
Acceptance is based on the number of read, write, and total transactions.
(17)
The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth
(18)
is based on W, A, and D channels.
System Interconnect
Send Feedback
I/F Width Clock
l4_main_clk
l4_main_clk
l4_main_clk
spi_m_clk
spi_m_clk
l4_main_clk
usb_mp_clk
nand_x_clk
nand_x_clk
l4_mp_clk
cfg_clk
l3_main_clk
Mastered By
L4 main bus master
L4 main bus master
L4 main bus master
L4 main bus master
L4 main bus master
L3 slave peripheral
switch
L3 slave peripheral
switch
L3 slave peripheral
switch
L3 slave peripheral
switch
L3 slave peripheral
switch
L3 interconnect
L3 interconnect
Interconnect Slave Properties
Acceptance Buffer
(17) Depth
(18)
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
16, 16, 32 2, 2, 2, 2, 2 AXI
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 2, 3 2, 2, 2, 32,
2
16, 16, 32 2, 2, 6, 6, 2 AXI
Altera Corporation
7-19
Type
APB
APB
APB
APB
APB
AHB
AXI
AXI
AHB
AXI