Altera cyclone V Technical Reference page 284

5-90
Pin Mux Control Group Register Descriptions
Bit
2
injdporta
1
injsporta
0
en
Pin Mux Control Group Register Descriptions
Controls Pin Mux selections NOTE: These registers should not be modified after IO configuration.There is
no support for dynamically changing the Pin Mux selections.
Offset:
0x400
EMACIO0
This register is used to control the peripherals connected to emac0_tx_clk Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
EMACIO1
This register is used to control the peripherals connected to emac0_tx_d0 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
EMACIO2
This register is used to control the peripherals connected to emac0_tx_d1 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
EMACIO3
This register is used to control the peripherals connected to emac0_tx_d2 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
EMACIO4
This register is used to control the peripherals connected to emac0_tx_d3 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
EMACIO5
This register is used to control the peripherals connected to emac0_rx_d0 Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
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Changing this bit from zero to one injects a double,
non-correctable error into the SDMMC RAM at Port
A. This only injects one double bit error into the
SDMMC RAM at Port A.
Changing this bit from zero to one injects a single,
correctable error into the SDMMC RAM at Port A.
This only injects one error into the SDMMC RAM at
Port A.
Enable ECC for SDMMC RAM
on page 5-107
on page 5-108
on page 5-109
on page 5-109
on page 5-110
on page 5-111
Description
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
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