Altera cyclone V Technical Reference page 908

cv_5v4
2016.10.28
onfi_timing_mode Fields
Bit
5:0
value
onfi_pgm_cache_timing_mode
Asynchronous Program Cache Timing modes supported by the connected ONFI device
Module Instance
nandregs
Offset:
0x3B0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
onfi_pgm_cache_timing_mode Fields
Bit
5:0
value
onfi_device_no_of_luns
Indicates if the device is an ONFI compliant device and the number of LUNS present in the device
NAND Flash Controller
Send Feedback
Name
The values in the field should be interpreted as
follows[list] [*]Bit 0 - Supports Timing mode 0. [*]Bit
1 - Supports Timing mode 1. [*]Bit 2 - Supports
Timing mode 2. [*]Bit 3 - Supports Timing mode 3.
[*]Bit 4 - Supports Timing mode 4. [*]Bit 5 - Supports
Timing mode 5.[/list]
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
The values in the field should be interpreted as
follows[list] [*]Bit 0 - Supports Timing mode 0. [*]Bit
1 - Supports Timing mode 1. [*]Bit 2 - Supports
Timing mode 2. [*]Bit 3 - Supports Timing mode 3.
[*]Bit 4 - Supports Timing mode 4. [*]Bit 5 - Supports
Timing mode 5.[/list]
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
onfi_pgm_cache_timing_mode
Access
Register Address
0xFFB803B0
21 20 19 18
5 4 3 2
value
RO 0x0
Access
13-87
Reset
RO 0x0
17 16
1 0
Reset
RO 0x0
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