Altera cyclone V Technical Reference page 965

cv_5v4
2016.10.28
• Response timeout
• Response CRC error
• Data receive timeout
• Response error
4. The DMA waits for the RX watermark to be reached before writing data to system memory, or the TX
watermark to be reached before reading data from system memory. The RX watermark represents the
number of bytes to be locally stored in the FIFO buffer before the DMA writes to memory. The TX
watermark represents the number of free bytes in the local FIFO buffer before the DMA reads data
from memory.
5. If the value of the programmable burst length (PBL) field is larger than the remaining amount of data
in the buffer, single transfers are initiated. If dual buffers are being used, and the second buffer contains
no data (buffer size = 0), the buffer is skipped and the descriptor is closed.
6. The OWN bit in descriptor is set to 0 by the internal DMA controller after the data transfer for one
descriptor is completed. If the transfer spans more than one descriptor, the DMA controller fetches the
next descriptor. If the transfer ends with the current descriptor, the internal DMA controller goes to
idle state after setting the
structure (dual buffer or chained), the appropriate starting address of descriptor is loaded. If it is the
second data buffer of dual buffer descriptor, the descriptor is not fetched again.
Abort During Internal DMA Transfer
If the host issues an SD/SDIO STOP_TRANSMISSION command (CMD12) to the card while data
transfer is in progress, the internal DMA controller closes the present descriptor after completing the data
transfer until a Data Transfer Over (DTO) interrupt is asserted. Once a STOP_TRANSMISSION
command is issued, the DMA controller performs single burst transfers.
• For a card write operation, the internal DMA controller keeps writing data to the FIFO buffer after
fetching it from the system memory until a DTO interrupt is asserted. This is done to keep the card
clock running so that the STOP_TRANSMISSION command is reliably sent to the card.
• For a card read operation, the internal DMA controller keeps reading data from the FIFO buffer and
writes to the system memory until a DTO interrupt is generated. This is required because DTO
interrupt is not generated until and unless all the FIFO buffer data is emptied.
Note: For a card write abort, only the current descriptor during which a STOP_TRANSMISSION
command is issued is closed by the internal DMA controller. The remaining unread descriptors are
not closed by the internal DMA controller.
Note: For a card read abort, the internal DMA controller reads the data out of the FIFO buffer and writes
them to the corresponding descriptor data buffers. The remaining unread descriptors are not
closed.
Fatal Bus Error Scenarios
A fatal bus error occurs when the master interface issues an error response. This error is a system error, so
the software driver must not perform any further setup on the controller. The only recovery mechanism
from such scenarios is to perform one of the following tasks:
• Issue a reset to the controller through the reset manager.
• Issue a program controller reset by writing to the controller reset bit (
register.
FIFO Buffer Overflow and Underflow
During normal data transfer conditions, FIFO buffer overflow and underflow does not occur. However, if
there is a programming error, a FIFO buffer overflow or underflow can result. For example, consider the
following scenarios.
SD/MMC Controller
Send Feedback
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Abort During Internal DMA Transfer
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controller_reset
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