Arbitration Between Direct/Indirect Access Controller And Stig - Altera cyclone V Technical Reference

15-10

Arbitration between Direct/Indirect Access Controller and STIG

request interface must be disabled. By default, the indirect watermark registers are set to zero, which
means the DMA peripheral request controller can issue DMA request as soon as possible.
For more information about the HPS DMA controller, refer to the DMA Controller chapter in volume 3 of
the Cyclone
Related Information
DMA Controller
Arbitration between Direct/Indirect Access Controller and STIG
When multiple controllers are active simultaneously, a fixed-priority arbitration scheme is used to
arbitrate between each interface and access the external FLASH. The fixed priority is defined as follows,
highest priority first.
1. The Indirect Access Write
2. The Direct Access Write
3. The STIG
4. The Direct Access Read
5. The Indirect Access Read
Each controller is back pressured while waiting to be serviced.
Configuring the Flash Device
For read and write accesses, software must initialize the device read instruction register (
device write instruction register (
that should be used as well as the instruction type, and whether the instruction uses single, dual or quad
pins for address and data transfer. To ensure the quad SPI controller can operate from a reset state, the
opcode registers reset to opcodes compatible with single I/O flash devices.
The quad SPI flash controller uses the instruction transfer width field (
set the instruction transfer width for both reads and writes. There is no
register. If instruction type is set to dual or quad mode, the address transfer width (
transfer width (
based on the instruction type. Thus, software can support the less common flash instructions where the
opcode, address, and data are sent on two or four lanes. For most instructions, the opcodes are sent
serially to the flash device, even for dual and quad instructions. One of the flash devices that supports
instructions that can send the opcode over two or four lanes is the Micron N25Q128. For reference,
15-2 Table 15-3
and
and write instruction, respectively, supported by the Micron N25Q128 device.
Table 15-2: Quad SPI Configuration for Micron N25Q128 Device (Read Instructions)
Instruction Lanes Used By
Read 1
Fast read 1
Dual 1
output fast
read
(DOFR)
Altera Corporation
V Device Handbook.
®
on page 16-1
devwr
) fields of both registers are redundant because the address and data type is
datawidth
show how software should configure the quad SPI controller for each specific read
Lanes Used to
Opcode Send Address
1
1
1
). These registers include fields to initialize the instruction opcodes
Lanes Used to instwidth
Send Data Value
1 0
1 0
2 0
) and the
devrd
) of the
instwidth devrd
field in the
instwidth devwr
) and data
addrwidth
addrwidth datawidth
Value
0 0
0 0
0 1
Quad SPI Flash Controller
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2016.10.28
register to
Table
Value