Altera cyclone V Technical Reference page 32

1-16
HPS Address Spaces
Figure 1-3: HPS Address Space Relationships
The window regions provide access to other address spaces. The thin black arrows indicate which address
space is accessed by a window region (arrows point to accessed address space). For example, accesses to
the ACP window in the L3 address space map to a 1 GB region of the MPU address space.
The SDRAM window in the MPU address space can grow and shrink at the top and bottom (short, blue
vertical arrows) at the expense of the FPGA slaves and boot regions. For specific details, refer to "MPU
Address Space".
The ACP window can be mapped to any 1 GB region in the MPU address space (blue vertical bidirectional
arrow), on gigabyte-aligned boundaries.
The following table shows the base address and size of each region that is common to the L3 and MPU
address spaces.
Table 1-2: Common Address Space Regions
Region Name
FPGA slaves
Peripheral
Lightweight FPGA slaves
Altera Corporation
Peripheral Region Lightweight
FPGA
FPGA
Slaves
Slaves
Region
ACP
Window
SDRAM
Window
RAM / SDRAM
L3
0xC0000000
0xFC000000
0xFF200000
Peripheral Region
FPGA
Slaves
Region
SDRAM
Window
Boot Region
(ROM/RAM/SDRAM)
FPGA-to-SDRAM
MPU
Base Address
4 GB
3 GB
SDRAM
2 GB
Region
1 GB
0 GB
Size
960 MB
64 MB
2 MB
Introduction to the Hard Processor System
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2016.10.28