Altera cyclone V Technical Reference page 129

3-18
stat
Offset:
0x0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
l4wd1rst l4wd0 mpuwd
rst 1rst
RW 0x0
RW
0x0
stat Fields
Bit
28
etrstalltimeout
27
fpgahstimeout
26
scanhstimeout
25
fpgamgrhstimeout
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
etrst fpgah scanh
allti stime stime
meout out out
RW RW RW
0x0 0x0 0x0
13 12 11 10
mpuwd Reser swwar
0rst ved mrst
RW RW RW
0x0 0x0 0x0
Name
A 1 indicates that Reset Manager's request to the ETR
(Embedded Trace Router) to stall its AXI master port
before starting a hardware sequenced warm reset
timed-out and the Reset Manager had to proceed with
the warm reset anyway.
A 1 indicates that Reset Manager's handshake request
to FPGA before starting a hardware sequenced warm
reset timed-out and the Reset Manager had to
proceed with the warm reset anyway.
A 1 indicates that Reset Manager's request to the
SCAN manager to stop driving JTAG clock to FPGA
CB before starting a hardware sequenced warm reset
timed-out and the Reset Manager had to proceed with
the warm reset anyway.
A 1 indicates that Reset Manager's request to the
FPGA manager to stop driving configuration clock to
FPGA CB before starting a hardware sequenced
warm reset timed-out and the Reset Manager had to
proceed with the warm reset anyway.
Bit Fields
25 24 23 22
fpgam sdrse Reserved
grhst lfref
imeou timeo
t ut
RW RW
0x0 0x0
9 8 7 6
fpgaw nrstp Reserved
armrs inrst
t
RW
RW 0x0
0x0
Description
21 20 19 18
cdbgr fpgad
eqrst bgrst
RW RW
0x0 0x0
5 4 3 2
swcol confi fpgac
drst gioco oldrs
ldrst t
RW
0x0 RW RW
0x0 0x0
Access
cv_5v4
2016.10.28
17 16
Reserved
1 0
nporp porvoltr
inrst st
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Reset Manager
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