Interactive Debugging Features - Altera cyclone V Technical Reference

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2016.10.28

Interactive Debugging Features

Each Cortex-A9 processor has built-in debugging capabilities, including six hardware breakpoints (two
with Context ID comparison capability) and four watchpoints. The interactive debugging features can be
controlled by external JTAG tools or by processor-based monitor code.
Related Information
ARM Infocenter
For more information about the interactive debugging system, refer to the Debug chapter of the Cortex-A9
Technical Reference Manual, available on the ARM Infocenter website.
L1 Caches
Cache memory that is closely coupled with an associated processor is called level 1, or L1 cache. Each
Cortex-A9 processor has two independent 32 KB L1 caches—one for instructions and one for data—
allowing simultaneous instruction fetches and data access. Each L1 cache is four-way set associative, with
32 bytes per line, and supports parity checking.
Note: A parity error cannot be recovered and is indicated by one of the parity error interrupt signals. On a
parity error interrupt, you can reset the system or perform further actions depending on the
indication of the interrupt signals.
Cache Latency
Latency for cache hits and misses varies.
The latency for an L1 cache hit is 1 clock. The latency for an L1 cache miss and L2 cache hit is 6 clocks best
case. Latency in the L2 cache can vary depending on other operations in the L2. Parity and ECC settings
have no effect on latency. A single-bit ECC error is corrected during the L2 read, but is not re-written to
the L2 RAM.
Preload Engine
The preload engine (PLE) is a hardware block that enables the L2 cache to preload selected regions of
memory.
The PLE signals the L2 cache when a cache line is needed in the L2 cache, by making the processor data
master port start fetching the data. The processor data master does not complete the fetch or return the
data to the processor. However, the L2 cache can then proceed to load the cache line. The data is only
loaded to the L2 cache, not to the L1 cache or processor registers.
The preload functionality is under software control. The following PLE control parameters must be
programmed:
• Programmed parameters, including the following:
• Base address
• Length of stride
• Number of blocks
• A valid bit
• TrustZone memory protection for the cache memory, with an NS (non-secure) state bit
• A translation table base (TTB) address
• An Address Space Identifier (ASID) value
Cortex-A9 Microprocessor Unit Subsystem
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Interactive Debugging Features
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