Quad Spi Flash Controller Programming Model - Altera cyclone V Technical Reference

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Quad SPI Flash Controller Programming Model

Protected area write attempt
Illegal data slave access detected
Transfer watermark reached
Receive overflow
TX FIFO not full
TX FIFO full
RX FIFO not empty
RX FIFO full
Indirect read partition overflow
Quad SPI Flash Controller Programming Model
Altera Corporation
Interrupt Source Description
A write to a protected area was attempted and
rejected.
An illegal data slave access has been detected. Data
slave wrapping bursts and the use of split and retry
accesses can cause this interrupt. It is usually an
indicator that soft masters in the FPGA fabric are
attempting to access the HPS in an unsupported
way.
The indirect transfer watermark level has been
reached.
This condition occurs only in legacy SPI mode.
When 0, no overflow has been detected. When 1, an
over flow to the RX FIFO buffer has occurred. This
bit is reset only by a system reset and cleared to zero
only when this register is written to. If a new write
to the RX FIFO buffer occurs at the same time as a
register is read, this flag remains set to 1.
This condition occurs only in legacy SPI mode.
When 0, the TX FIFO buffer is full. When 1, the TX
FIFO buffer is not full.
This condition occurs only in legacy SPI mode.
When 0, the TX FIFO buffer is not full. When 1, the
TX FIFO buffer is full.
This condition occurs only in legacy SPI mode.
When 0, the RX FIFO buffer is empty. When 1, the
RX FIFO buffer is not empty.
This condition occurs only in legacy SPI mode.
When 0, the RX FIFO buffer is not full. When 1, the
RX FIFO buffer is full.
Indirect Read Partition of SRAM is full and unable
to immediately complete indirect operation
cv_5v4
2016.10.28
Quad SPI Flash Controller
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