Altera cyclone V Technical Reference page 74

cv_5v4
2016.10.28
31 30
15 14
Reserved saten faste
RW
0x1
0x0
misc Fields
Bit
14
saten
13
fasten
12:1
bwadj
0
bwadjen
mpuclk
Contains settings that control clock mpu_clk generated from the C0 output of the Main PLL. Only reset by
a cold reset.
Module Instance
clkmgr
Offset:
0x48
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Clock Manager
Send Feedback
29 28 27 26
13 12 11 10
n
RW
Name
Enables saturation behavior.
Enables fast locking circuit.
Provides Loop Bandwidth Adjust value.
If set to 1, the Loop Bandwidth Adjust value comes
from the Loop Bandwidth Adjust field. If set to 0, the
Loop Bandwidth Adjust value equals the M field
divided by 2 value of the VCO Control Register. The
M divided by 2 is the upper 12 bits (12:1) of the M
field in the VCO register.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
bwadj
RW 0x1
Description
Base Address
mpuclk
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD04048
2-37
17 16
1 0
bwadjen
RW 0x0
Reset
RW 0x1
RW 0x0
RW 0x1
RW 0x0
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