Security - Altera cyclone V Technical Reference

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Security

Related Information
System Manager
For more information about enabling or disabling these features, refer to the System Manager chapter.
Security
Slave Security
The interconnect enforces security through the slave settings. The slave settings are controlled by the
address region control registers accessible through the GPV registers. Each L3 and L4 slave has its own
security check and programmable security settings. After reset, every slave of the interconnect is set to a
secure state (referred to as boot secure). The only accesses allowed to secure slaves are by secure masters.
The GPV can only be accessed by secure masters. The security state of the interconnect is not accessible
through the GPV as the security registers are write-only. Any nonsecure accesses to the GPV receive a
response, and no register access is provided. Updates to the security settings through the GPV do
DECERR
not take effect until all transactions to the affected slave have completed.
Related Information
http://infocenter.arm.com
For more information about AXI terms such as
Interconnect (NIC-301) Technical Reference Manual, revision r2p3, which you can download from the
ARM Infocenter website.
Master Security
Masters of the system interconnect are either secure, nonsecure, or the security is set on a per transaction
basis. The DAP and Ethernet masters only perform secure accesses. The L2 cache master 0, FPGA-to-HPS-
bridge, and DMA perform secure and nonsecure accesses on a per transaction basis. All other system
interconnect masters perform nonsecure accesses.
Accesses to secure slaves by unsecure masters result in a response of
reach the slave.
All masters are secure at reset.
Related Information
System Interconnect Master Properties
Controlling Quality of Service from Software
You can programmatically configure the QoS generator for each initiator through the QoS registers.
Note: Before accessing the registers for any QoS generator, you must ensure that the corresponding
peripheral is not in reset. Otherwise, the register access results in a bus error, causing a CPU fault.
Related Information
L3 (NIC-301) GPV Registers Address Map
Information about the GPV
Altera Corporation
on page 5-1
on page 7-16
registers
write_qos
, , and
DECERR WRAP INCR
DECERR
on page 7-23
, refer to the AMBA Network
and the transaction does not
System Interconnect
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cv_5v4
2016.10.28