Altera cyclone V Technical Reference page 865

13-44
program_wait_cnt
load_wait_cnt Fields
Bit
15:0
value
program_wait_cnt
Wait count value for Program operation
Module Instance
nandregs
Offset:
0x30
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
Number of clock cycles after issue of load operation
before NAND Flash Controller polls for status. This
values is of relevance for status polling mode of
operation and has been provided to minimize
redundant polling after issuing a command. After a
load command, the first polling will happen after this
many number of cycles have elapsed and then on
polling will happen every int_mon_cyccnt cycles. The
default values is equal to the default value of int_
mon_cyccnt
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RW 0x1F4
Access
Register Address
0xFFB80030
21 20 19 18
5 4 3 2
NAND Flash Controller
cv_5v4
2016.10.28
Reset
RW 0x1F4
17 16
1 0
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