Altera cyclone V Technical Reference page 758

11-20
Memory Protection
Bits
5:0
2. The
protruleid
3. The
protruledata
Once the registers are configured, they can be committed to the internal protection table by programming
the
ruleoffset
Secure and non-secure regions are specified by rules containing a starting address and ending address with
1 MB boundaries for both addresses. You can override the port defaults and allow or disallow all transac‐
tions.
The following table lists the fields that you can specify for each rule.
Table 11-8: Fields for Rules in Memory Protection Table
Field
Valid
Port Mask
(28)
AxID_low (28)
AxID_high (28)
Address_low
Address_high
Although AxID and Port Mask could be redundant, including both in the table allows possible compression
(28)
of rules. If masters connected to a port do not have contiguous AxIDs, a port-based rule might be more
efficient than an AxID-based rule, in terms of the number of rules needed.
Altera Corporation
When this bit is set to 1, deny accesses from FPGA-to-SDRAM ports 0 through 5
during a default transaction.
When this bit is clear, allow accesses from FPGA-to-SDRAM ports 0 through 5
during a default transaction.
register gives the bounds of the AxID value that allows an access
register configures the specific security characteristics for a rule.
field and setting the
writerule
Width
1
10
12
12
12
12
Description
bit in the
protruledwr
Set to 1 to activate the rule. Set to 0 to deactivate the rule.
Specifies the set of ports to which the rule applies, with one
bit representing each port, as follows: bits 0 to 5 correspond
to FPGA fabric ports 0 to 5, bit 6 corresponds to AXI L3
interconnect read, bit 7 is the CPU read, bit 8 is L3 intercon‐
nect write, and bit 9 is the CPU write.
Low transfer AxID of the rules to which this rule applies.
Incoming transactions match if they are greater than or equal
to this value. Ports with smaller AxIDs have the AxID shifted
to the lower bits and zero padded at the top.
High transfer AxID of the rules to which this rule applies.
Incoming transactions match if they are less than or equal to
Points to a 1MB block and is the lower address. Incoming
addresses match if they are greater than or equal to this value.
Upper limit of address. Incoming addresses match if they are
less than or equal to this value.
register.
Description
this value.
SDRAM Controller Subsystem
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cv_5v4
2016.10.28