Altera cyclone V Technical Reference page 992

14-46
Clock Setup
If bit 4 is set to 1, the card device supports ATA mode.
2. Send the SWITCH_FUNC (CMD6) command, setting the ATA bit (bit 4) of the EXT_CSD register
slice 191 (CMD_SET) to 1.
This command selects ATA mode and activates the ATA command set.
3. You can verify the currently selected mode by reading it back from byte 191 of the EXT_CSD register.
4. Skip to
If the card device does not support ATA mode, it might be an MMC card or a CE-ATA v1.0 card.
Proceed to the
card device.
Determine whether the card is a CE-ATA 1.0 card device or an MMC card device by sending the
RW_REG command.
If a response is received and the response data contains the CE-ATA signature, the card is a CE-ATA 1.0
card device. Otherwise, the card is an MMC card device.
Clock Setup
The following registers of the SD/MMC controller allow software to select the desired clock frequency for
the card:
•
clksrc
•
clkdiv
•
clkena
The controller loads these registers when it receives an update clocks command.
Changing the Card Clock Frequency
To change the card clock frequency, perform the following steps:
1. Before disabling the clocks, ensure that the card is not busy with any previous data command. To do so,
verify that the
2. Reset the
3. Reset the
4. Set the following bits in the
•
update_clk_regs_only
•
wait_prvdata_complete
transfer is complete
•
start_cmd
5. Wait until the
clock modification completes. The controller does not set the
upon command completion. The controller might signal a hardware lock error if it already has another
command in the queue. In this case, return to
For information about hardware lock errors, refer to the "Interrupt and Error Handling" chapter.
6. Reset the
(
perpllgrp
7. In the control register (
the drive clock phase shift select (
the required phase shift value.
8. Set the
9. Set the
10.Set the
Altera Corporation
step 5 of the Identifying the Connected Card Type section.
next section
to determine whether the card is a CE-ATA 1.0 card device or an MMC
bit of the status register (
data_busy
bit of the
cclk_enable
register to 0.
clksrc
cmd
—Specifies the update clocks command
—Ensures that clock parameters do not change until any ongoing data
†
—Initiates the command
and
start_cmd update_clk_regs_only
bit to 0 in the
sdmmc_clk_enable
).
) of the SDMMC controller group (
ctrl
bit in the
sdmmc_clk_enable
register of the controller to the correct divider value for the required clock frequency.
clkdiv
bit of the
cclk_enable clkena
status
register to 0, to disable the card clock generation.
clkena
register to 1:
†
bits change to 0. There is no interrupt when the
Step 4.
register of the clock manager peripheral PLL group
enable
) and sample clock phase shift select (
drvsel
register of the clock manager
Enable
register to 1, to enable the card clock generation.
) is 0.
†
bit in the
command_done
) in the system manager, set
sdmmcgrp
smplsel
perpllgrp
cv_5v4
2016.10.28
register
rintsts
) bits to specify
group to 1.
SD/MMC Controller
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