Altera cyclone V Technical Reference page 723

cv_5v4
2016.10.28
TPIU
Figure 10-6: Trace Clock and Trace Data Width
Table 10-4: TPIU Signals
The following table lists the signal descriptions between the TPIU and FPGA.
h2f_tpiu_clk_ctl
h2f_tpiu_data[32]
h2f_tpiu_clock_in
h2f_tpiu_clock
CoreSight Debug and Trace
Send Feedback
Signal
Selects whether trace data is captured using the internal TPIU
clock, which is the
dbg_trace_clk
manager; or an external clock provided as an input to the TPIU
from the FPGA.
0 - use
h2f_tpiu_clock_in
1 - use internal clock
Note: When the FPGA is powered down or not configured the
TPIU uses the internal clock.
32 bit trace data bus to the FPGA. Trace data changes on both
edges of
h2f_tpiu_clock
Note: When the FPGA is powered down or not configured, the
TPIU sends the lower 8-bits trace data to I/Os.
Clock from the FPGA used to capture trace data.
Clock output from TPIU
Description
signal from the clock
.
10-13
TPIU
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