Altera cyclone V Technical Reference page 206

Hard processor system
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5-12
System Manager Module Address Map
Warm Boot from On-Chip RAM Group
Register
enable
on page 5-59
datastart
on page 5-
60
length
on page 5-61
execution
on page 5-
62
crc
on page 5-62
Boot ROM Hardware Register Group
Register
ctrl
on page 5-63
SDMMC Controller Group
Register
ctrl
on page 5-65
l3master
on page 5-
66
NAND Flash Controller Register Group
Register
bootstrap
on page 5-
68
l3master
on page 5-
69
Altera Corporation
Offset
Width Acces
s
0xE0
32
RW
0xE4
32
RW
0xE8
32
RW
0xEC
32
RW
0xF0
32
RW
Offset
Width Acces
s
0x100
32
RW
Offset
Width Acces
s
0x108
32
RW
0x10C
32
RW
Offset
Width Acces
s
0x110
32
RW
0x114
32
RW
Reset Value
Enable Register
0x0
Data Start Register
0x0
Length Register
0x0
Execution Register
0x0
Expected CRC Register
0xE763552A
Reset Value
Boot ROM Hardware Control
0x2
Register
Reset Value
Control Register
0x0
SD/MMC L3 Master HPROT
0x3
Register
Reset Value
Bootstrap Control Register
0x0
NAND L3 Master AxCACHE
0x0
Register
cv_5v4
2016.10.28
Description
Description
Description
Description
System Manager
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