Altera cyclone V Technical Reference page 812

11-74
Port Sum of Weight Register Register Descriptions
remappriority Fields
Bit
7:0
priorityremap
Port Sum of Weight Register Register Descriptions
This register is used to configure the DRAM burst operation scheduling.
Offset:
0xb0
mpweight_0_4
This register is used to configure the DRAM burst operation scheduling.
mpweight_1_4
This register is used to configure the DRAM burst operation scheduling.
mpweight_2_4
This register is used to configure the DRAM burst operation scheduling.
mpweight_3_4
This register is used to configure the DRAM burst operation scheduling.
mpweight_0_4
This register is used to configure the DRAM burst operation scheduling.
Module Instance
sdr
Offset:
0x50B0
Access:
RW
Altera Corporation
Name
Each bit of this field represents a priority level. If bit N
in the
priorityremap
transaction with absolute user priority of N jumps to
the front of the single port queue and is serviced
ahead of any tranactions in the queue. For example, if
bit 5 is set in the
remappriority
with a
register is serviced ahead of any other transaction
already in the single port queue.
on page 11-74
on page 11-75
on page 11-76
on page 11-76
0xFFC20000
Description
field is set, then any port
priorityremap
register, then any port transaction
value of 0x5 in the
userpriority
Base Address
Access
field of the
mppriority
Register Address
0xFFC250B0
SDRAM Controller Subsystem
cv_5v4
2016.10.28
Reset
RW 0x0
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