Altera cyclone V Technical Reference page 916

cv_5v4
2016.10.28
Module Instance
nandregs
Offset:
0x420
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
page_ pipe_ rst_
xfer_inc cmd_ comp
err
RW 0x0
RW 0x1
0x0
intr_en0 Fields
Bit
15
page_xfer_inc
14
pipe_cmd_err
13
rst_comp
12
INT_act
11
unsup_cmd
10
locked_blk
NAND Flash Controller
Send Feedback
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
INT_ unsup locke
act _cmd d_blk
RW RW RW RW
0x0 0x0 0x0
Name
For every page of data transfer to or from the device,
this bit will be set.
A pipeline command sequence has been violated. This
occurs when Map 01 page read/write address does not
match the corresponding expected address from the
pipeline commands issued earlier.
A reset command has completed on this bank
R/B pin of device transitioned from low to high
An unsupported command was received. This
interrupt is set when an invalid command is received,
or when a command sequence is broken.
The address to program or erase operation is to a
locked block and the operation failed due to this
reason
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
pipe_ erase progr load_
cpybc _comp am_ comp
k_ comp
RW RW
cmd_
0x0 RW 0x0
comp
0x0
RW
0x0
Description
intr_en0
Register Address
0xFFB80420
21 20 19 18
5 4 3 2
erase progr time_ dma_
_fail am_ out cmd_
fail comp
RW RW
0x0 RW 0x0 RW
0x0 0x0
Access
13-95
17 16
1 0
Reser ecc_
ved uncor_
err
RW 0x0
Reset
RW 0x0
RW 0x0
RW 0x1
RW 0x0
RW 0x0
RW 0x0
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