Altera cyclone V Technical Reference page 57

2-20
Clock Usage By Module
Module Name
DMA controller
FPGA manager
HPS-to-FPGA bridge
FPGA-to-HPS bridge
Lightweight HPS-to-FPGA
bridge
Quad SPI flash controller
SD/MMC controller
EMAC 0
Altera Corporation
System Clock Name
l4_main_clk
dbg_at_clk
l4_mp_clk
cfg_clk
l4_mp_clk
l3_main_clk
l4_mp_clk
l3_main_clk
l4_mp_clk
l4_mp_clk
l4_mp_clk
qspi_clk
l4_mp_clk
sdmmc_clk
l4_mp_clk
emac0_clk
osc1_clk
Use
DMA
Synchronous to the STM module
Synchronous to the quad SPI
flash
Control block (CB) data
interface and configuration data
slave
Control slave
Data slave
Global programmer's view
(GPV) slave
Data master
GPV slave
GPV masters and the data and
GPV slave
Control slave
Reference for serialization
Master and slave
SD/MMC internal logic
Master
EMAC 0 internal logic
IEEE 1588 timestamp
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cv_5v4
2016.10.28
Clock Manager