Altera cyclone V Technical Reference page 620

8-38
periph_id_0
31 30
15 14
periph_id_4 Fields
Bit
7:0
periph_id_4
periph_id_0
Peripheral ID0
Module Instance
lwhps2fpgaregs
Offset:
0x1FE0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
periph_id_0 Fields
Bit
7:0
pn7to0
periph_id_1
Peripheral ID1
Altera Corporation
29 28 27 26
13 12 11 10
Reserved
Name
JEP106 continuation code
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Part Number [7:0]
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFF400000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
21 20 19 18
5 4 3 2
periph_id_4
RO 0x4
Access
Register Address
0xFF401FE0
21 20 19 18
5 4 3 2
pn7to0
RO 0x1
Access
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x4
17 16
1 0
Reset
RO 0x1
HPS-FPGA Bridges
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