Altera cyclone V Technical Reference page 805

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
fpgaportrst Fields
Bit
13:0
portrstn
protportdefault
This register controls the default protection assignment for a port. Ports which have explicit rules which
define regions which are illegal to access should set the bits to pass by default. Ports which have explicit
rules which define legal areas should set the bit to force all transactions to fail. Leaving this register to all
zeros should be used for systems which do not desire any protection from the memory controller.
Module Instance
sdr
Offset:
0x508C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
SDRAM Controller Subsystem
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This register should be written to with a 1 to enable
the selected FPGA port to exit reset. Writing a bit to a
zero will stretch the port reset until the register is
written. Read data ports are connected to bits 3:0,
with read data port 0 at bit 0 to read data port 3 at bit
3. Write data ports 0 to 3 are mapped to 4 to 7, with
write data port 0 connected to bit 4 to write data port
3 at bit 7. Command ports are connected to bits 8 to
13, with command port 0 at bit 8 to command port 5
at bit 13. Expected usage would be to set all the bits at
the same time but setting some bits to a zero and
others to a one is supported.
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
portrstn
RW 0x0
Description
Base Address
protportdefault
21 20 19 18
5 4 3 2
Access
Register Address
0xFFC2508C
11-67
17 16
1 0
Reset
RW 0x0
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