Altera cyclone V Technical Reference page 52

cv_5v4
2016.10.28
Table 2-9: Flash Controller Clocks
System Clock Name
qspi_clk
nand_x_clk
nand_clk
sdmmc_clk
SDRAM Clock Group
The SDRAM clock group consists of a PLL and clock gating. The clocks in the SDRAM clock group are
derived from the SDRAM PLL. The SDRAM PLL can be programmed to be sourced from the
pin, the
HPS_CLK2
The FPGA fabric must be configured with an image that provides the
it as the clock source. If the FPGA must be reconfigured and the
for the SDRAM clock group, an alternate clock source must be selected prior to reconfiguring the FPGA.
The counter outputs from the SDRAM PLL can be gated off directly under software control. The divider
values for each clock are set by registers in the clock manager.
Clock Manager
Send Feedback
Freq
uency
Up to 432 MHz
Up to 250 MHz
/4
nand_x_clk
Up to 200 MHz
pin, or the
f2h_sdram_ref_clk
Divided From
Peripheral PLL C2, main
PLL C3, or
f2h_periph_
ref_clk
Peripheral PLL C3, main
PLL C4, or
f2h_periph_
ref_clk
Peripheral PLL C3, main
PLL C4, or
f2h_periph_
ref_clk
Peripheral PLL C3, main
PLL C4, or
f2h_periph_
ref_clk
clock provided by the FPGA fabric.
f2h_sdram_ref_clk
f2h_sdram_ref_clk
2-15
SDRAM Clock Group
Constraints and Notes
Clock for quad SPI,
typically 108 and
80 MHz
NAND flash controller
master and slave clock
Main clock for NAND
flash controller, sets
base frequency for
NAND transactions
• Less than or equal
to memory
maximum operating
frequency
• 45% to 55% duty
cycle
• Typical frequencies
are 26 and 52 MHz
• SD/MMC has a
subclock tree
divided down from
this clock
HPS_CLK1
before selecting
is the clock source
Altera Corporation