Altera cyclone V Technical Reference page 78

cv_5v4
2016.10.28
cfgs2fuser0clk
Contains settings that control clock cfg_s2f_user0_clk generated from the C5 output of the Main PLL.
Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk. Only reset by a cold reset.
Module Instance
clkmgr
Offset:
0x5C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
cfgs2fuser0clk Fields
Bit
8:0
cnt
en
Contains fields that control clock enables for clocks derived from the Main PLL. 1: The clock is enabled. 0:
The clock is disabled. Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0x60
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Clock Manager
Send Feedback
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Divides the VCO frequency by the value+1 in this
field.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
cfgs2fuser0clk
Register Address
0xFFD0405C
21 20 19 18
5 4 3 2
cnt
RW 0xF
Access
Register Address
0xFFD04060
2-41
17 16
1 0
Reset
RW 0xF
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