Altera cyclone V Technical Reference page 872

cv_5v4
2016.10.28
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
cache_read_enable Fields
Bit
0
flag
prefetch_mode
Enables read data prefetching to faster performance
Module Instance
nandregs
Offset:
0xC0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
NAND Flash Controller
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
[list][*]1 - Cache read supported [*]0 - Cache read
not supported[/list]
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
prefetch_burst_length
RW 0x0
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
prefetch_mode
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB800C0
21 20 19 18
5 4 3 2
Reserved
13-51
17 16
1 0
flag
RW 0x0
Reset
RW 0x0
17 16
1 0
prefetch
_en
RW 0x1
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