Altera cyclone V Technical Reference page 314

5-120
FLASHIO3
FLASHIO2 Fields
Bit
1:0
sel
FLASHIO3
This register is used to control the peripherals connected to sdmmc_d1 Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x45C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
FLASHIO3 Fields
Bit
1:0
sel
Altera Corporation
Name
Select peripheral signals connected sdmmc_d0. 0 :
Pin is connected to GPIO/LoanIO number 38. 1 : Pin
is connected to Peripheral signal not applicable. 2 :
Pin is connected to Peripheral signal USB0.D2. 3 : Pin
is connected to Peripheral signal SDMMC.D0.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected sdmmc_d1. 0 :
Pin is connected to GPIO/LoanIO number 39. 1 : Pin
is connected to Peripheral signal not applicable. 2 :
Pin is connected to Peripheral signal USB0.D3. 3 : Pin
is connected to Peripheral signal SDMMC.D1.
Description
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Access
Register Address
0xFFD0845C
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
System Manager
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